Reduction of interrupt service latency in multi-processor systems
US11200098B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 19, 2019 |
| Grant date | Dec 14, 2021 |
| Priority date | — |
| Expiry date | Feb 19, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/526
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique for operating a system including a plurality of processors and a shared resource includes executing a first instruction by a first processor of the plurality of processors. The first instruction generates a reservation of the shared resource for the first processor. The technique includes, after generating the reservation of the shared resource for the first processor, executing a spin lock by the first processor until successful execution of a second instruction acquires a lock of the shared resource. The technique includes disabling interrupts of the first processor in response to an indicator of the successful execution of the second instruction. The first instruction may be a load and reserve instruction and the second instruction may be a conditional store instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.