Command based on-die termination for high-speed NAND interface
US11200190B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2020 |
| Grant date | Dec 14, 2021 |
| Priority date | — |
| Expiry date | Apr 21, 2040 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, apparatus and methods are provided for multi-drop multi-load NAND interface topology where a number of NAND flash devices share a common data bus with a NAND controller. A method for controlling on-die termination in a non-volatile storage device may comprise receiving a chip enable signal on a chip enable signal line from a controller, receiving an on-die termination (ODT) command on a data bus from the controller while the chip enable signal is on, decoding the on-die termination command and applying termination resistor (RTT) settings in the ODT command to a selected non-volatile storage unit at the non-volatile storage device to enable ODT for the selected non-volatile storage unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.