Pixel array substrate
US11200826B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 6, 2020 |
| Grant date | Dec 14, 2021 |
| Priority date | — |
| Expiry date | Aug 6, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/0281
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A pixel array substrate, including scanning line pads, data line pads, scanning lines, data lines, gate transmission lines, pixels, a data line signal chip, and a scanning line signal chip, is provided. The scanning lines extend along a first direction. The data lines and the gate transmission lines extend along a second direction. The data lines are electrically connected to the data line pads. The scanning lines are electrically connected to the scanning line pads through the gate transmission lines. A ratio of a number of rows of pixels arranged in the first direction to a number of rows of pixels arranged in the second direction is X:Y. Each pixel includes m sub-pixels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.