Semiconductor device
US11201087B2 · kind B2 · utility
0Cited by
9References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2020 |
| Grant date | Dec 14, 2021 |
| Priority date | — |
| Expiry date | Apr 2, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes forming an active pattern on a substrate, the active pattern comprising first semiconductor patterns and second semiconductor patterns, which are alternately stacked, forming a capping pattern on a top surface and a sidewall of the active pattern, performing a deposition process on the capping pattern to form an insulating layer, and forming a sacrificial gate pattern intersecting the active pattern on the insulating layer. The capping pattern has a crystalline structure and is in physical contact with sidewalls of the first semiconductor patterns and sidewalls of the second semiconductor patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.