Semiconductor package mounted substrate
US11201108B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2019 |
| Grant date | Dec 14, 2021 |
| Priority date | — |
| Expiry date | Dec 30, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10734
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package mounted board includes a printed circuit board on which a plurality of first pads and a plurality of second pads are disposed on one surface, and a semiconductor package disposed on the one surface of the printed circuit board and including a plurality of third pads and a plurality of fourth pads. A plurality of first electrical connection structures electrically connect the plurality of first pads and the plurality of third pads, and one or more second electrical connection structures electrically connect the plurality of second pads and the plurality of fourth pads. The plurality of first pads are disposed to correspond to and overlap/align with the plurality of third pads from each other, and the plurality of second pads are disposed to be staggered and offset with respect to the plurality of fourth pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.