System on chip
US11201150B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 17, 2020 |
| Grant date | Dec 14, 2021 |
| Priority date | — |
| Expiry date | Apr 28, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0135
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A system on chip includes first to third nanowires extending in a second direction, first to third gate lines respectively surrounding the first to third nanowires, each of the first to third gate lines extending in a first direction across the second direction, a gate isolation region cutting the first to third gate lines and extending in the second direction, a first gate contact formed on the second gate line arranged between the first gate line and the third gate line, and electrically connecting the cut second gate line, a second gate contact formed on the first gate line, a third gate contact formed on the third gate line, a first metal line electrically connecting the second gate contact and the third gate contact; and a second metal line electrically connected to the first gate contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.