Efuse memory cell, eFuse memory array and using method thereof, and eFuse system
US11201161B2 · kind B2 · utility
Assignees
Inventor
Key dates
| Filing date | Nov 23, 2020 |
| Grant date | Dec 14, 2021 |
| Priority date | — |
| Expiry date | Nov 23, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B20/25
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An eFuse memory cell, an eFuse memory array and a using method thereof, and an eFuse system are provided. In one form, an eFuse memory cell includes: a programming transistor, where a source of the programming transistor is grounded; a first electric fuse having a first terminal and a second terminal opposite to the first terminal, where the first terminal is connected to a drain of the programming transistor; one or more second electric fuses connected in parallel to each other, where each of the second electric fuses is connected in parallel with the first electric fuse, the second electric fuse has a third terminal and a fourth terminal opposite to the third terminal, and the third terminal is connected to the drain of the programming transistor; a word line connected to a gate of the programming transistor; a first programming bit line connected to the second terminal of the first electric fuse; and one or more second programming bit lines in a one-to-one correspondence with the second electric fuses, the second programming bit line being connected to the fourth terminal of the corresponding second electric fuse. The eFuse memory cell provided in the present disclosure has an o…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.