Detector circuit and system for galvanically isolated transmission of digital signals
US11201766B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 27, 2019 |
| Grant date | Dec 14, 2021 |
| Priority date | — |
| Expiry date | Mar 27, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45588
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A detector circuit for galvanically isolated transmission of digital signals. The detector circuit includes two differential signal inputs, one input common-mode voltage connection, one alternating voltage coupling, and one differential stage. The detector circuit also includes one operating voltage connection, one operating ground connection, one signal output, one bias current connection, and one rectifier stage. The alternating current coupling includes two capacitors and two resistors. The differential stage includes a first n-channel transistor and a second n-channel transistor. The bias current connection is connected to the differential stage via a third n-channel transistor. The bias current connection is connected to the rectifier stage via a fourth n-channel transistor and a fifth n-channel transistor. The rectifier stage includes five p-channel transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.