Processing method and device for cache synchronous exception
US11202227B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2018 |
| Grant date | Dec 14, 2021 |
| Priority date | — |
| Expiry date | Dec 20, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04W80/02
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Disclosed in the present disclosure are a processing method and device for a cache synchronous exception, for solving the problem that no solution for a compression check failure is available in the prior art. According to embodiments of the present disclosure, when caches are out of synchronization, a caching failure notification message is sent to a transmitting device; a reset processing is carried out on a compressed cache area, and a reset instruction is sent; and then subsequent data packet transmission is carried out by using reset cache areas. In the present disclosure, after it is determined that the caches are out of synchronization, the caching failure notification message is sent; the transmitting device performs a reset processing on the compressed cache area, and notifies a receiving device to carry out a reset processing on a decompressed cache area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.