Reprogrammable quantum processor architecture incorporating quantum error correction
US11203526B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2019 |
| Grant date | Dec 21, 2021 |
| Priority date | — |
| Expiry date | Jun 19, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/44
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A novel and useful quantum computing machine architecture that includes a classic computing core as well as a quantum computing core. A programmable pattern generator executes sequences of instructions that control the quantum core. In accordance with the sequences, a pulse generator functions to generate the control signals that are input to the quantum core to perform quantum operations. A partial readout of the quantum state in the quantum core is generated that is subsequently re-injected back into the quantum core to extend decoherence time. Access gates control movement of quantum particles in the quantum core. Errors are corrected from the partial readout before being re-injected back into the quantum core. Internal and external calibration loops calculate error syndromes and calibrate the control pulses input to the quantum core. Control of the quantum core is provided from an external support unit via the pattern generator or can be retrieved from classic memory where sequences of commands for the quantum core are stored a priori in the memory. A cryostat unit functions to provide several temperatures to the quantum machine including a temperature to cool the quantum compu…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.