Retention-aware data tiering algorithm for hybrid storage arrays
US11204705B2 · kind B2 · utility
3Cited by
9References
20Claims
0Family size
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Key dates
| Filing date | Mar 5, 2019 |
| Grant date | Dec 21, 2021 |
| Priority date | — |
| Expiry date | Jul 4, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7211
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array controller includes memory media scanning logic to sample a bit error rate of memory blocks of a first memory device. A data management logic may then move data from the first memory device to a second memory device if the bit error rate matches a threshold level. The threshold level is derived from a configurable data retention time parameter for the first memory device. The configurable data retention time parameter may be received from a user or determined utilizing various known machine learning techniques.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.