Memory error detection and correction
US11204826B2 · kind B2 · utility
9Cited by
8References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 8, 2019 |
| Grant date | Dec 21, 2021 |
| Priority date | — |
| Expiry date | Aug 8, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device, such as a MRAM device, includes a plurality of memory macros, where each includes an array of memory cells and a first ECC circuit configured to detect data errors in the respective memory macro. A second ECC circuit that is remote from the plurality of memory macros is communicatively coupled to each of the plurality of memory macros. The second ECC circuit is configured to receive the detected data errors from the first ECC circuits of the plurality of memory macros and correct the data errors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.