Systems and methods for an ECC architecture with prioritized task queues
US11204829B2 · kind B2 · utility
1Cited by
2References
16Claims
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Key dates
| Filing date | Mar 26, 2019 |
| Grant date | Dec 21, 2021 |
| Priority date | — |
| Expiry date | Oct 10, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, apparatus and methods are provided for an error correction code (ECC) architecture with reduced decoding latency in error control. An apparatus may comprise control circuitry configured to receive a status report that a decoding task has failed, determine that a higher priority is needed for a re-decoding task, generate a NAND read task having a second priority level higher than a first priority level of the failed decoding task, and generate an ECC re-decoding task having the second priority level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.