Writebacks of prefetched data
US11204878B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 8, 2020 |
| Grant date | Dec 21, 2021 |
| Priority date | — |
| Expiry date | Oct 8, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/502
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus is provided that includes a memory hierarchy comprising a plurality of caches and a memory. Prefetch circuitry acquires data from the memory hierarchy before the data is explicitly requested by processing circuitry configured to execute a stream of instructions. Writeback circuitry causes the data to be written back from a higher level cache of the memory hierarchy to a lower level cache of the memory hierarchy and tracking circuitry tracks a proportion of entries that are stored in the lower level cache of the memory hierarchy having been written back from the higher level cache of the memory hierarchy, that are subsequently explicitly requested by the processing circuitry in response to one of the instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.