Cache line cleanup for prevention of side channel attack
US11204995B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2019 |
| Grant date | Dec 21, 2021 |
| Priority date | — |
| Expiry date | Jun 2, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/034
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Examples of techniques for cache line cleanup for prevention of side channel attack are described herein. An aspect includes determining, by a rollback control unit, a start of a speculative execution in a computer processor. Another aspect includes setting a field in a speculative buffer of the computer processor based on a load or a store to a cache line of a cache being performed by the speculative execution. Another aspect includes determining a failure of the speculative execution. Another aspect includes, based on the failure of the speculative execution, traversing the speculative buffer to determine the set field and performing a cleanup of the cache line based on the set field in the speculative buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.