Avoiding data exchange in gate operation for quantum computing gates on a chip
US11205030B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 3, 2019 |
| Grant date | Dec 21, 2021 |
| Priority date | — |
| Expiry date | Mar 7, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N10/80
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-implemented method performed by one or more computing nodes for simulating a gate operation of quantum computing is disclosed. In the method, a problem having 2n size is divided into a plurality of sub-problems, each of which has 2m size. A first index table for storing a first identifier is prepared for each sub-problem. In response to a request for a gate operation involving exchanges of quantum amplitudes that are designated by a target qubit at least in part, a determination is made as to whether a first condition regarding at least the target qubit and m is satisfied or not. In response to the first condition being satisfied, corresponding first identifiers in the first index table are swapped in place of the exchanges of the quantum amplitudes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.