Stack packages
US11205614B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2020 |
| Grant date | Dec 21, 2021 |
| Priority date | — |
| Expiry date | Apr 30, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/16238
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stack package may include a first substrate package, a second substrate package, an interposer and at least one semiconductor chip. The first substrate package may include a plurality of first pads isolated from direct contact with each other by a first pitch. The second substrate package may be under the first substrate package. The second substrate package may include a plurality of second pads isolated from direct contact with each other by a second pitch. The second pitch may be different from the first pitch. The interposer may be above the first substrate package. The interposer may include a plurality of third pads isolated from direct contact with each other by a third pitch. The semiconductor chip may be arranged above the interposer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.