Integrated circuit devices and methods of manufacturing the same
US11205649B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2020 |
| Grant date | Dec 21, 2021 |
| Priority date | — |
| Expiry date | Jun 4, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/364
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Integrated circuit devices may include a fin-type active area, a semiconductor liner contacting a side wall of the fin-type active area and including a protrusion portion protruding outward from the fin-type active area in the vicinity of an edge of an upper surface of the fin-type active area, and an isolation layer spaced apart from the fin-type active area with the semiconductor liner therebetween. To manufacture the integrated circuit devices, a crystalline semiconductor layer covering the fin-type active area with a first thickness and an amorphous semiconductor layer covering the mask pattern with a second thickness may be formed, an extended crystalline semiconductor layer covering the mask pattern may be formed by crystalizing the amorphous semiconductor layer, and a semiconductor liner including a protrusion portion may be formed from the extended crystalline semiconductor layer and the crystalline semiconductor layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.