Memory devices
US11205682B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2019 |
| Grant date | Dec 21, 2021 |
| Priority date | — |
| Expiry date | Jun 20, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B63/30
Abstract
A memory device includes first conductive lines extending in a first direction, second conductive lines extending in a second direction, and a plurality of memory cells each arranged between the first and second conductive lines and each including a variable resistance memory layer and a switch material pattern. The switch material pattern includes an element injection area arranged in an outer area of the switch material pattern, and an internal area covered by the element injection area. The internal area contains a first content of at least one element from arsenic (As), sulfur (S), selenium (Se), and tellurium (Te), the element injection area contains a second content of the at least one element from As, S, Se, and Te, and the second content has a profile in which a content of the at least one element decreases away from the at least one surface of the switch material pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.