Evaluating cyber-risk in synchrophasor systems
US11206287B2 · kind B2 · utility
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25Claims
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Key dates
| Filing date | Jan 29, 2019 |
| Grant date | Dec 21, 2021 |
| Priority date | — |
| Expiry date | Oct 5, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2463/121
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Technology related to evaluating cyber-risk for synchrophasor systems is disclosed. In one example of the disclosed technology, a method includes generating an event tree model of a timing-attack on a synchrophasor system architecture. The event tree model can be based on locations and types of timing-attacks, an attack likelihood, vulnerabilities and detectability along a scenario path, and consequences of the timing-attack. A cyber-risk score of the synchrophasor system architecture can be determined using the event tree model. The synchrophasor system architecture can be adapted in response to the cyber-risk score.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.