Methods and devices for testing comparators
US11209482B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2020 |
| Grant date | Dec 28, 2021 |
| Priority date | — |
| Expiry date | Nov 30, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2215
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A device for a system on a chip (SOC), the device includes: a comparator that includes a first input port, a second input port, and an output port. A first input signal and a second input signal are split into N bit pairs that include one bit from the first input signal and one bit from the second input signal. The comparator is configured so a mismatch between the first input signal and the second input signal causes an output signal to assume a first expected state. The device further comprises a test controller to perform a first operability test by mismatching the N bit pairs and verifying that the output signal assumes the first expected state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.