Low power active load
US11209485B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Jan 8, 2018 |
| Grant date | Dec 28, 2021 |
| Priority date | — |
| Expiry date | Apr 7, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2844
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An active load circuit that includes a diode bridge having first through fourth nodes, wherein a voltage buffer is connected with the first node, a source current mirror is connected with the second node, the third node is configured for connection to a device under test (DUT), and a sink current mirror is connected with the fourth node. A first current mirror is connected with the source current mirror, and a second current mirror is connected with the sink current mirror. A first differential pair is connected with the first current mirror and includes an input connected with the DUT and a second input connected with the input voltage. A second differential pair is connected with the second current mirror and includes a first input connected with the DUT and a second input connected with the input voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.