Error recovery storage for non-associative memory
US11210186B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2019 |
| Grant date | Dec 28, 2021 |
| Priority date | — |
| Expiry date | Oct 15, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus comprises a non-associative memory comprising a plurality of storage locations, and error recovery storage to store at least one error recovery entry providing a recovery value for a corresponding storage location of the non-associative memory. Control circuitry is responsive to a non-associative memory read request specifying a target address of a storage location of the non-associative memory, when the error recovery storage includes a valid matching error recovery entry for which the corresponding storage location is the storage location identified by the target address, to return the recovery value stored in the valid matching error recovery entry as a response to the non-associative memory read request, instead of information stored in the storage location identified by the target address. This enables the apparatus to continue to function even if hard errors occur in a storage location of the non-associative memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.