PCIe controller and loopback data path using PCIe controller
US11210247B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 11, 2018 |
| Grant date | Dec 28, 2021 |
| Priority date | — |
| Expiry date | Aug 8, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A PCIe controller and a loopback path using the PCIe controller. The PCIe controller includes: a transport layer transmission module, a transport layer reception module, a memory access module, and a memory, wherein the transport layer transmission module includes a first loopback control module, the transport layer reception module includes a second loopback control module, and the first loopback control module is coupled to the second loopback control module; the memory access module is coupled to the transport layer transmission module and the transport layer reception module, and the memory access module is also coupled to the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.