Patent · US Active

Timing assistant for dynamic voltage drop impact on setup/hold constraints

US11210444B1 · kind B1 · utility

4Cited by

11References

26Claims

0Family size

Assignee

ANSYS, INC. · US

Inventors

Norman Chang · Fremont, US
Hao Zhuang · Shanghai, CN
Ganesh Tsavatapalli · Bengaluru, IN
Joao Geada · Chelmsford, US
Sankar Ramachandran · Kanchinakote, IN
Rahul Rajan · Thrissur, IN
Ying-Shiun Li · Pleasanton, US
Yaowei Jia · San Jose, US
Mathew Joseph Kaipanatu · Thrissur, IN
Suresh Kumar Mantena · Darsi, IN

Key dates

Filing date	Jun 21, 2019
Grant date	Dec 28, 2021
Priority date	—
Expiry date	Sep 10, 2039

Classification

Technology area (CPC G)Physics
CPC primaryG06F2119/12
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Example systems and methods are disclosed for performing a timing analysis on a circuit design. A plurality of switching scenarios are identified for the circuit design. One or more predictive models are applied to predict a subset of the plurality of switching scenarios that are likely to cause timing paths with critical timing problems. A dynamic voltage analysis is performed on timing paths based on the subset of switching scenarios. The one or more predictive models are applied to predict a set of critical timing paths based on the subset of switching scenarios that are likely to cause critical timing problems, the one or more predictive models taking into account the dynamic voltage analysis. A timing analysis is the performed on the set of critical timing paths.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.