Display controller having auxilary circuits in two FPGAs in connection
US11210992B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 21, 2019 |
| Grant date | Dec 28, 2021 |
| Priority date | — |
| Expiry date | Sep 4, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2370/20
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A display controller is provided. The display controller includes n field-programmable gate arrays (FPGAs) (n is an integer greater than 1). A respective one of the n FPGAs includes a first input circuit and an output circuit and a first process circuit connected between the first input circuit and the output circuit. The first input circuit is configured to receive a respective one first sub-image corresponding to the respective one of the n FPGAs. The n first sub-images are combined to form one frame of initial image. The first process circuit is configured to enhance image-resolution of the respective one first sub-image to obtain a respective one second sub-image and the output circuit is configured to deliver the respective one second sub-image corresponding to the respective one of the n FPGAs to a timing-controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.