High frame rate display
US11211020B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2019 |
| Grant date | Dec 28, 2021 |
| Priority date | — |
| Expiry date | May 9, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/0295
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A display may have rows and columns of pixels. Gate lines may be used to supply gate signals to rows of the pixels. Data lines may be used to supply data signals to columns of the pixels. The data lines may include alternating even and odd data lines. Data lines may be organized in pairs each of which includes one of the odd data lines and an adjacent one of the even data lines. Demultiplexer circuitry may be configured dynamically during data loading and pixel sensing operations. During data loading, data from display driver circuitry may be supplied, alternately to odd pairs of the data lines and even pairs of the data lines. During sensing, the demultiplexer circuitry may couple a pair of the even data lines to sensing circuitry in the display driver circuitry and then may couple a pair of the odd data lines to the sensing circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.