Method of addressing dissimilar etch rates
US11211258B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 8, 2020 |
| Grant date | Dec 28, 2021 |
| Priority date | — |
| Expiry date | Apr 8, 2040 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB81C2201/0132
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for DRIE matched release and/or the mitigation of photo resist pooling, comprising: depositing a first mask layer over a first surface of a silicon substrate; exposing a first portion and second portion of the first mask layer to a first etch process, wherein the exposing forms a first exposed layer; depositing a second mask layer over the first mask layer; exposing a third portion of the second mask layer to a second etch process, wherein the exposing forms a second exposed mask layer, and wherein the third portion overlaps the first portion of the first mask layer; developing the second mask layer and etching the third portion of the second mask layer and developing the first portion of the first mask layer; etching the first portion of the first mask layer to a first depth; and developing the first mask layer to reveal exposed portions of the first mask layer and etching the second portion of the silicon substrate to a second depth.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.