Semiconductor package with terminal pattern for increased channel density
US11211315B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 13, 2017 |
| Grant date | Dec 28, 2021 |
| Priority date | — |
| Expiry date | Feb 27, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10734
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Described examples include an apparatus, including: a substrate having a first surface configured to mount at least one integrated circuit and having a second surface opposite the first surface, the second surface having a plurality of terminals arranged in rows and columns, and at least one row of the plurality of terminals disposed adjacent a first side and extending generally along the length of the substrate arranged in a pattern extending along a longitudinal line, the pattern including a first group of consecutive terminals extending in a first direction at a first angle to the longitudinal line and directed towards an interior of the substrate, a second group of consecutive terminals extending in a second direction at a second angle and extending towards the periphery of the substrate, and a third group of consecutive ones of the terminals extending from the second group in the first direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.