Bump layout for coplanarity improvement
US11211318B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2019 |
| Grant date | Dec 28, 2021 |
| Priority date | — |
| Expiry date | Jun 21, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/384
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes receiving a first design for conductive bumps on a first surface of an interposer, the conductive bumps in the first design having a same cross-section area; grouping the conductive bumps in the first design into a first group of conductive bumps in a first region of the first surface and a second group of conductive bumps in a second region of the first surface, where a bump pattern density of the second region is lower than that of the first region; forming a second design by modifying the first design, where modifying the first design includes modifying a cross-section area of the second group of conductive bumps in the second region; and forming the conductive bumps on the first surface of the interposer in accordance with the second design, where after being formed, the first group of conductive bumps and the second group of conductive bumps have different cross-section areas.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.