Power MOS device with low gate charge and a method for manufacturing the same

US11211486B2 · kind B2 · utility

Assignee

• University of Electronic Science and Technology of China · CN

Inventors

• Ming Qiao · Chengdu, CN
• Zhengkang Wang · Chengdu, CN
• Shida Dong · Chengdu, CN
• Bo Zhang · Shanghai, CN

Key dates

• Filing date: Aug 28, 2020
• Grant date: Dec 28, 2021
• Expiry date: Aug 28, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/2527

Abstract

A power MOS device with low gate charge and a method for manufacturing the same. The device includes an M-shaped gate structure, which reduces the overlapped area between control gate electrode and split gate electrode. A low-k material is introduced to reduce dielectric constant of the isolation medium material. The combination of the M-shaped gate structure and low-k material can reduce parasitic capacitance Cgs of the device, thereby increasing switching speed and reducing switching losses.