FPGA chip with distributed multifunctional layer structure
US11211933B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2018 |
| Grant date | Dec 28, 2021 |
| Priority date | — |
| Expiry date | Jan 8, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17796
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An FPGA chip includes one functional unit, one pre-allocation manager, and wiring segments. The functional unit includes a first module CPE and a second module PLF. The pre-allocation manager may be connected by means of one of the wiring segments. By configuring one pre-allocation manager, data transmission directions of the wiring segments may be changed. The functional unit is connected to one pre-allocation manager by means of a conventional line. The first module CPE and the second module PLF which are adjacent in the same functional unit are connected by means of a cross-connection line. The second functional modules are interconnected by means of a conventional routing system. Different functional blocks can be connected to each other from any position of a circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.