All-digital voltage monitor (ADVM) with single-cycle latency
US11211935B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2020 |
| Grant date | Dec 28, 2021 |
| Priority date | — |
| Expiry date | Sep 14, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An all-digital voltage monitor (ADVM) generates a multi-bit output code that changes in proportion to a voltage being monitored, by leveraging the voltage impact on a gate delay. ADVM utilizes a simple delay chain, which receives a clock-cycle-long pulse every clock cycle, such that the monitored supply voltage is sampled for one full cycle every cycle. The outputs of all delay cells of the delay chain collectively represents a current voltage state as a digital thermometer code. In AVDM, a voltage droop event thus results in a decrease in the output code from a nominal value, while an overshoot results in an increase in the output code.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.