Parallelized decoding of variable-length prefix codes
US11211945B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2020 |
| Grant date | Dec 28, 2021 |
| Priority date | — |
| Expiry date | Oct 29, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/6005
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and systems are provided for decoding variable-length codes in a parallel process. A stream of variable-length code words is divided into fixed length words. A plurality of parallel sets of decoder circuits each receive, in parallel, a current fixed length word and a prior fixed length word. Each decoder circuit has a respective fixed leftover bit-count. Each decoder circuit generates a respective output that may include a decoded symbol and a new leftover bit-count. Each respective output is determined based on the respective current fixed length word, the respective prior fixed length word, and the respective fixed leftover bit-count. A set of selected decoder circuit outputs is generated for each set of the parallel sets of decoder circuits based on a set of first leftover bit-counts. One output from each set of selected decoder circuit outputs is selected as a final output based on a second prior leftover bit-count.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.