Multi-level secure ethernet switch
US11212257B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2018 |
| Grant date | Dec 28, 2021 |
| Priority date | — |
| Expiry date | Sep 14, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L9/3236
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A multi-level secure switch includes a security enforcer logic chip, a switch chip, a management processor, and a plurality of physical ports. The security enforcer logic chip is configured to receive and transmit a plurality of data packets, each having an associated security level. The switch chip is configured to transmit the data packets to and receive the data packets from the security enforcer logic chip. The management processor is configured to provide security parameters to the security enforcer logic chip. Each of the plurality of physical ports have an associated security threshold and transmit and receive data packets to and from the security enforcer logic chip. The security enforcer logic chip is configured to transmit a data packets to a physical port only when the security level associated with data packet is compatible with the security threshold associated with the physical ports.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.