Minimizing conflicts in multiport banked memory arrays
US11216212B2 · kind B2 · utility
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17Claims
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Key dates
| Filing date | Mar 19, 2019 |
| Grant date | Jan 4, 2022 |
| Priority date | — |
| Expiry date | Mar 19, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0683
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various embodiments are provided for managing multiport banked memory arrays in a computing system by a processor. One or more conflicts may be eliminated in a multiport banked memory array upon receiving one or more write operations, read operations, or a combination thereof according to a selected priority and access protocol.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.