Scheduler for vector processing operator readiness
US11216307B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 30, 2019 |
| Grant date | Jan 4, 2022 |
| Priority date | — |
| Expiry date | Jun 18, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a processor and an operator readiness circuit. The processor may be configured to schedule one or more operators used to process a plurality of vectors based on one or more status signals indicating a readiness state of the one or more operators. The operator readiness circuit may be configured to (i) compare a target position and an actual position of each operand associated with the one or more operators to determine a readiness state of each operand, (ii) update the readiness state of the operands using a plurality of state machines, and (iii) generate the one or more status signals indicating the readiness state of the one or more operators based on the readiness state of each operand associated with the one or more operators.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.