Data protection circuit of chip, chip, and electronic device
US11216593B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 14, 2019 |
| Grant date | Jan 4, 2022 |
| Priority date | — |
| Expiry date | May 14, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/78
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data protection circuit of a chip, a chip, and an electronic device, where the data protection circuit performs bit width expansion and scrambling processing on a first alarm signal using an operation circuit to obtain a second alarm signal, and outputs the second alarm signal to a processing circuit. The processing circuit performs descrambling processing after receiving the second alarm signal to obtain a descrambling result. When the second alarm signal is attacked, the descrambling fails, and the descrambling result is an active level. The processing circuit outputs the descrambling result to a reset request circuit, and the reset request circuit generates a reset request signal according to the descrambling result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.