Method of fabricating a semiconductor device
US11217457B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2020 |
| Grant date | Jan 4, 2022 |
| Priority date | — |
| Expiry date | Jun 27, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/78
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a semiconductor device including preparing a substrate including a wafer inner region and a wafer edge region, the wafer inner region including a chip region and a scribe lane region, sequentially stacking a mold layer and a supporting layer on the substrate, forming a first mask layer on the supporting layer, the first mask layer including a first stepped region on the wafer edge region, forming a step-difference compensation pattern on the first stepped region, forming a second mask pattern including openings, on the first mask layer and the step-difference compensation pattern, and sequentially etching the first mask layer, the supporting layer, and the mold layer using the second mask pattern as an etch mask to form a plurality of holes in at least the mold layer may be provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.