Semiconductor arrangement and method of manufacture
US11217487B2 · kind B2 · utility
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1References
20Claims
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Assignee
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Key dates
| Filing date | Nov 19, 2019 |
| Grant date | Jan 4, 2022 |
| Priority date | — |
| Expiry date | Nov 19, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a semiconductor arrangement includes forming a first gate structure over a first active region. The first gate structure includes a first conductive layer. An etch process is performed using a process gas mixture to recess the first gate structure and define a recess. The etch process comprises a first phase to form a polymer layer over the first conductive layer and to modify a portion of the first conductive layer to form a modified portion of the first conductive layer and a second phase to remove the polymer layer and to remove the modified portion of the first conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.