Thin-film transistor and manufacturing method therefor, array substrate and display device
US11217697B2 · kind B2 · utility
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3References
19Claims
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Key dates
| Filing date | Apr 20, 2018 |
| Grant date | Jan 4, 2022 |
| Priority date | — |
| Expiry date | Apr 20, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An active layer of the thin-film transistor includes a channel region, a source region and a drain region. The source region and the drain region are respectively arranged on both sides of the channel region, and the channel region includes a polycrystalline silicon structure doped with a fifth group element. A potential difference between the source-drain region and the channel region is increased by doping with the fifth group element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.