Patent · US Active

Configurable built-in self-test for an all digital phase locked loop

US11218153B1 · kind B1 · utility

7Cited by

5References

20Claims

0Family size

Assignee

NXP B.V. · NL

Inventors

Ulrich Moehlmann · Hamburg, DE
Lars Henrik Heinbockel · Moisburg, DE
Torsten Gerhardt · London, GB
Christian Scherner · Hamburg, DE

Key dates

Filing date	Oct 29, 2020
Grant date	Jan 4, 2022
Priority date	—
Expiry date	Oct 29, 2040

Classification

Technology area (CPC H)Electricity
CPC primaryH03L2207/50
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A built-in self-test (BIST) block is provided that is incorporated into an all-digital phase locked loop (ADPLL) located on chip with the ADPLL. The BIST performs testing functions without need for support external to the chip. Test setup, test control, and test evaluation are performed entirely on chip. The BIST provides information regarding success or failure of the testing and can provide error information regarding test cases that do not pass successfully.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.