Clock and data recovery devices with fractional-N PLL
US11218156B2 · kind B2 · utility
0Cited by
7References
10Claims
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Assignee
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Key dates
| Filing date | Sep 4, 2020 |
| Grant date | Jan 4, 2022 |
| Priority date | — |
| Expiry date | Sep 4, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.