Tracking analog-to-digital converter with adaptive slew rate boosting
US11218161B1 · kind B1 · utility
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15References
17Claims
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Key dates
| Filing date | Nov 16, 2020 |
| Grant date | Jan 4, 2022 |
| Priority date | — |
| Expiry date | Nov 16, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/464
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A tracking ADC with adaptive slew rate boosting can dynamically adjust one or more of its operational parameters in response to detecting a slew rate limit condition. In some embodiments, slew rate boosting can include increasing the value of a digital error signal in response to detection of a slew rate limit condition. In other embodiments, slew rate boosting can include increasing a clock frequency of the tracking ADC in response to detection of a slew rate limit condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.