Hardware based packet replication at tail end node
US11218336B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 2020 |
| Grant date | Jan 4, 2022 |
| Priority date | — |
| Expiry date | Apr 7, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/02
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Aspects of the disclosed technology address limitations relating to packet replication for multi-destination traffic, by providing methods for performing hardware-based replication in network infrastructure devices, such as switches. In some aspects, application specific integrated circuits (ASICs) resident in physical devices can be used to perform packet replication. Depending on implementation, a hardware-based replication process can include steps for receiving a first packet that includes a first outer header containing first address information, receiving a second packet including a second outer header containing a hardware replication flag, forwarding the first packet to all virtual tunnel endpoints (VTEPs) connected with the TOR switch, and performing hardware replication for the second packet based on the hardware replication flag to generate one or more unicast packets. Systems and machine readable media are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.