Foveated rendering in tiled architectures
US11222397B2 · kind B2 · utility
2Cited by
6References
24Claims
0Family size
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Key dates
| Filing date | Dec 23, 2016 |
| Grant date | Jan 11, 2022 |
| Priority date | — |
| Expiry date | Dec 23, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2210/36
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
This disclosure describes examples for foveation rendering. A graphics processing unit (GPU) may render image content for each tile at different sizes as part of the rendering pass after a binning pass in which the GPU determined to which tiles vertices of primitives belong. The GPU may upsample the rendered image content based on the size at which GPU rendered the image content, and output the upsampled image content for later display.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.