Circuit architecture to derive higher mux from lower mux design

US11222670B2 · kind B2 · utility

Assignee

• Arm Limited · GB

Inventors

• Lalit Gupta · Kanchinakote, IN
• Nicolaas Klarinus Johannes Van Winkelhoff · Meylan, FR
• El Mehdi Boujamaa · Grasse, FR
• Bo Zheng · Sunnyvale, US
• Fakhruddin Ali Bohra · Austin, US
• Cyrille Dray · Hillsboro, US
• Ashish Bhardwaj · Hyderabad, IN
• Durgesh Kumar Dubey · Noida, IN

Key dates

• Filing date: Dec 10, 2019
• Grant date: Jan 11, 2022
• Expiry date: Dec 10, 2039

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C2207/108
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Various implementations described herein are directed to an implementation of a higher order multiplexer using lower order multiplexers. In an embodiment, the implementation requires a slight modification to the existing circuitry design of the lower multiplexers. A plurality of multiplexers may be coupled with each other such that a common input port and output port is formed. Using an enable signal, only one of the coupled multiplexers may be enabled at a time while the remaining multiplexers are switched off. Therefore, upon receiving a select signal indicating an address of a memory cell, the lower multiplexers coupled together function as a higher order multiplexer in selecting the appropriate column corresponding to the memory cell.