Patent · US Active

Integrated power semiconductor device and method for manufacturing the same

US11222890B2 · kind B2 · utility

0Cited by
1References
12Claims
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Assignee

Inventors

Key dates

Filing dateApr 3, 2020
Grant dateJan 11, 2022
Priority date
Expiry dateMay 14, 2040

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D84/856
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

An integrated power semiconductor device, includes devices integrated on a single chip. The devices include a vertical high voltage device, a first high voltage pLDMOS device, a high voltage nLDMOS device, a second high voltage pLDMOS device, a low voltage NMOS device, a low voltage PMOS device, a low voltage NPN device, and a low voltage diode device. A dielectric isolation is applied to the first high voltage pLDMOS device, the high voltage nLDMOS device, the second high voltage pLDMOS device, the low voltage NMOS device, the low voltage PMOS device, the low voltage NPN device, and the low voltage diode device. A multi-channel design is applied to the first high voltage pLDMOS device, and the high voltage nLDMOS device. A single channel design is applied to the second high voltage pLDMOS device.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.