Semiconductor device and a fabrication method thereof
US11222897B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2020 |
| Grant date | Jan 11, 2022 |
| Priority date | — |
| Expiry date | Mar 16, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/485
Abstract
A semiconductor device including a substrate having a cell region and a peripheral region; a cell gate structure disposed on the cell region; a first impurity region and a second impurity region, arranged on first and second sides of the cell gate structure in the cell region; a bit line structure disposed on the cell gate structure and connected to the first impurity region; a peripheral gate structure disposed on the peripheral region; a peripheral capping layer disposed on the peripheral region, covering the peripheral gate structure, and having an upper surface at substantially the same level as an upper end of the bit line structure; and a cell contact structure disposed on the second impurity region, and having a conductive barrier and a contact material layer on the conductive barrier, wherein the conductive barrier covers the upper end of the bit line structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.