Heterojunction transistor with vertical structure
US11222967B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 14, 2017 |
| Grant date | Jan 11, 2022 |
| Priority date | — |
| Expiry date | May 31, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/513
Abstract
The invention concerns a heterojunction field-effect transistor comprising a stack of first and second III-N type semiconducting layers forming an electron gas or hole layer; a first conduction electrode in electrical contact with the gas layer and a second conduction electrode; a separation layer positioned vertically in line with the first electrode and under the second semiconducting layer; a third semiconducting layer arranged under the separation layer and in electrical contact with the second electrode; a conductive element in electrical contact with the gas layer and electrically connecting the third semiconducting layer and the gas layer; and a control gate positioned between the conductive element and the first conduction electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.